Power MOSFETs are rated for maximum reverse voltage BVdss. When it is operated above BVdss threshold it causes high electric fields in the reversed P-N junction thus causing avalanche current to commence. This high power dissipation causes temperature rise and eventually causes potential damage.
Power MOSFETs like any other semiconductor devices have parasitic components. The failure in Avalanche mode is caused from forward biasing the parasitic BJT as shown in the above figure. This happens when the temperature rise during avalanche current dissipation causes a sufficient voltage drop across Rb to turn-on the parasitic BJT which result in potentially damaging result. Today’s MOSFET designs are focused on reducing the effect of Rb and Avalanche Testing was developed to validate it can survive the avalanche mode ratings.
DUT is turned-ON at the beginning charging the Inductor (L) at a linear rate while the Drain Current (ID) is continuously being monitored. When the required ID is reached, the DUT is then turned-OFF causing the Inductor to dissipate all of its stored energy and causing the DUT to reach its breakdown rating. The DUT will remain in breakdown until all of the energy is dissipated. The Single-Pulse Avalanche Energy is calculated as:
From the equation it can be evident that the energy is very much dependent on the VDS which in most cases varies and curved during the discharging phase. Another issue is when used for low voltage devices the VDS-VDD tend to become very small which leads to more test inaccuracies.
To overcome these issues a modified Unclamped Inductive Switching test was developed.
A high-speed switch and a blocking diode were added to the original test method. The high-speed switch is turned-OFF simultaneously as the DUT decoupling the VDD from the circuit. The blocking diode becomes the path for the circulating current and thus keeping the voltage drop in the Inductor equal to the Avalanche voltage. The Energy can then be calculated simply as:
Notice that the energy is no longer dependent on VDD and VDS-VDD.
One limitation of this configuration however is the test time can be very long with low voltage and high energy Avalanche devices. Long test time during production means higher cost of testing.
For example: testing a device with BVDSS of 20V and with a required Inductor of 30mH and 80A will mean that VDD can only be set <=20V. 20V VDD can take about 120ms to charge the 30mH inductor to 80A. So the test time is 120ms plus tester overhead so the test time can be as long as 140ms which is very costly for production testing.
A modified UIS with DUT-ON is shown above. The DUT is switched ON first before the high-speed VDD switch thus allowing a VDD setting much higher than the BVDSS of the device. The VDD can be set to whatever is the maximum capability of the tester.
For a Max VDD of 75V and using the previous example of 30mH and 80A, the charging time will be only around 32ms which is a 75% reduction!
Some testers simply rely on Functionality check before and after the Avalanche test to screen-out failures. Others have a more stringent screening that are based on the measurement obtained from the actual avalanche waveforms and are tested against calculated limits:
This sophisticated screening requires the waveforms of VDS and ID to be digitized so it can be processed to obtain the required measurements.