The popularity of GaN semiconductor devices is increasing in today’s market due to the emergence of new technologies and the rising application areas where GaN devices outshine and outperform their Silicon counterparts. GaN devices are providing huge opportunities in vertical market sectors such as automotive (hybrid electric vehicles), Information and Communication Technology (Cloud servers), and Aerospace (Hi-Rel).
Along with the high performance and attractive operating characteristics of GaN devices come the practical considerations for deployment which bring unique reliability challenges. In order to overcome the barriers of reliability and repeatable performance characteristics, and the reluctance of designers to design their systems with GaN devices, GaN manufacturers can provide well characterized and tested devices. In addition, detailed data sheets with performance specifications and operating condition ranges go a long way in providing confidence to design engineers that their systems will operate and perform as designed.
Performance and Reliability in GaN devices has thus become a huge area of interest for automatic test equipment providers and GaN device manufacturers. It is well accepted in the industry that the current collapse effect limits the performance and reliability of GaN devices. The current collapse phenomenon appears as a transient and recoverable reduction in drain current after the application of high Drain-Source voltage. This phenomenon can be characterized with a measurement technique called “Dynamic On-Resistance: RDS(on)”.
GaN device manufacturers must have this test data in order to adequately test and characterize the high performance devices that they are providing to the systems design marketplace. Moreover, the necessary tests must be able to be executed quickly, consistently, and reliably in a production test environment. Because the current collapse effect is the most significant impediment to reliable and consistent device operation, the Dynamic On-Resistance test can and should be utilized as a pass/fail or quality binning criteria.
Another important design parameter is threshold shift. We also can measure the gate threshold voltage VGS(th) accurately, without applying higher voltage to the gate. This allows us to measure the threshold shift repeatably.
Another key factor we can offer is testing of both enhancement mode (e-Mode) and depletion mode (d-Mode) devices with thresholds to 35V and more.
Testing of high performance GaN devices differs from that of Silicon or SiC because of the parasitic devices that are present in the substrate due to the defects caused by lattice mismatch between the GaN epitaxial layer and the Silicon or Silicon Carbon substrate. These parasitic devices cause the GaN device to behave differently under varying test conditions. The results are not often trustworthy because the number and behavior of the parasitics vary across the wafer, as well as wafer to wafer. The problem is compounded by the GaN device behaving differently over time. The history of earlier conditions on the device as well as the timing of those conditions changes the behavior of the device, so accurate and repeatable timing of the testing is essential.
Test sequence is also of concern, because performing multiple tests in a different order, or with a different time period between tests, will also produce different results.
This test, when executed correctly, can determine whether a particular device is “good” or not. Different devices exhibit this behavior to different extents depending on the number and location of the substrate defects. Devices must be tested in fabrication, on the wafer, to be able to determine if the entire wafer, or parts of the wafer are not performing acceptably. The RDS(on) test can be done as part of a test sequence in a single pass on a wafer.
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